Anantha P. Chandrakasan
Joseph F. and Nancy P. Keithley Professor of Electrical Engineering, Department Head, MIT Electrical Engineering and Computer Science
Energy-Efficient System Design for Wearable Platforms
Anantha P. Chandrakasan
The use of low-power sensors and electronics can greatly enhance the environment awareness for the visually impaired. For example, using a Time-of-Flight camera, which captures depth information, along with a processor which implements computer vision techniques, can assist a user in obstacle avoidance. A key challenge in implementing such a navigation system is to implement the sensing, processing, energy conversion, and communication in an energy-efficient fashion. To reduce energy requires a system-level approach. The use of duty-cycling of the ToF sensor using user and environment state, can dramatically reduce energy consumption by reducing illumination power. The use of a hardwired processor for the computation can reduce energy by two orders of magnitude compared to software implementations. To maximize energy savings, the computation should exploit data statistics and low-voltages using architectural parallelism. The energy source and management are critical in managing user experience. Integrating wireless power and energy harvesting allows the user to extend system use time. The overall system-level trade-offs will be described in the presentation.
Anantha P. Chandrakasan received the B.S, M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1989, 1990, and 1994 respectively. Since September 1994, he has been with the Massachusetts Institute of Technology, Cambridge, where he is currently the Joseph F. and Nancy P. Keithley Professor of Electrical Engineering. He was a co-recipient of several awards including the 1993 IEEE Communications Society’s Best Tutorial Paper Award, the IEEE Electron Devices Society’s 1997 Paul Rappaport Award for the Best Paper in an EDS publication during 1997, the 1999 DAC Design Contest Award, the 2004 DAC/ISSCC Student Design Contest Award, the 2007 ISSCC Beatrice Winner Award for Editorial Excellence and the ISSCC Jack Kilby Award for Outstanding Student Paper (2007, 2008, 2009). He received the 2009 Semiconductor Industry Association (SIA) University Researcher Award. He is the recipient of the 2013 IEEE Donald O. Pederson Award in Solid-State Circuits. He is an elected member of the National Academy of Engineering.His research interests include micro-power digital and mixed-signal integrated circuit design, wireless microsensor system design, portable multimedia devices, energy efficient radios and emerging technologies. He is a co-author of Low Power Digital CMOS Design (Kluwer Academic Publishers, 1995), Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd edition), and Sub-threshold Design for Ultra-Low Power Systems (Springer 2006). He is also a co-editor of Low Power CMOS Design (IEEE Press, 1998), Design of High-Performance Microprocessor Circuits (IEEE Press, 2000), and Leakage in Nanometer CMOS Technologies (Springer, 2005).He has served as a technical program co-chair for the 1997 International Symposium on Low Power Electronics and Design (ISLPED), VLSI Design ’98, and the 1998 IEEE Workshop on Signal Processing Systems. He was the Signal Processing Sub-committee Chair for ISSCC 1999-2001, the Program Vice-Chair for ISSCC 2002, the Program Chair for ISSCC 2003, the Technology Directions Sub-committee Chair for ISSCC 2004-2009, and the Conference Chair for ISSCC 2010-2014. He is the Conference Chair for ISSCC 2015. He was an Associate Editor for the IEEE Journal of Solid-State Circuits from 1998 to 2001. He served on SSCS AdCom from 2000 to 2007 and he was the meetings committee chair from 2004 to 2007. He was the Director of the MIT Microsystems Technology Laboratories from 2006 to 2011. Since July 2011, he is the Head of the MIT EECS Department.